Line data Source code
1 : /* SPDX-License-Identifier: GPL-2.0-only */
2 : /*
3 : * Based on arch/arm/include/asm/processor.h
4 : *
5 : * Copyright (C) 1995-1999 Russell King
6 : * Copyright (C) 2012 ARM Ltd.
7 : */
8 : #ifndef __ASM_PROCESSOR_H
9 : #define __ASM_PROCESSOR_H
10 :
11 : /*
12 : * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
13 : * no point in shifting all network buffers by 2 bytes just to make some IP
14 : * header fields appear aligned in memory, potentially sacrificing some DMA
15 : * performance on some platforms.
16 : */
17 : #define NET_IP_ALIGN 0
18 :
19 : #define MTE_CTRL_GCR_USER_EXCL_SHIFT 0
20 : #define MTE_CTRL_GCR_USER_EXCL_MASK 0xffff
21 :
22 : #define MTE_CTRL_TCF_SYNC (1UL << 16)
23 : #define MTE_CTRL_TCF_ASYNC (1UL << 17)
24 : #define MTE_CTRL_TCF_ASYMM (1UL << 18)
25 :
26 : #ifndef __ASSEMBLY__
27 :
28 : #include <linux/build_bug.h>
29 : #include <linux/cache.h>
30 : #include <linux/init.h>
31 : #include <linux/stddef.h>
32 : #include <linux/string.h>
33 : #include <linux/thread_info.h>
34 :
35 : #include <vdso/processor.h>
36 :
37 : #include <asm/alternative.h>
38 : #include <asm/cpufeature.h>
39 : #include <asm/hw_breakpoint.h>
40 : #include <asm/kasan.h>
41 : #include <asm/lse.h>
42 : #include <asm/pgtable-hwdef.h>
43 : #include <asm/pointer_auth.h>
44 : #include <asm/ptrace.h>
45 : #include <asm/spectre.h>
46 : #include <asm/types.h>
47 :
48 : /*
49 : * TASK_SIZE - the maximum size of a user space task.
50 : * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
51 : */
52 :
53 : #define DEFAULT_MAP_WINDOW_64 (UL(1) << VA_BITS_MIN)
54 : #define TASK_SIZE_64 (UL(1) << vabits_actual)
55 : #define TASK_SIZE_MAX (UL(1) << VA_BITS)
56 :
57 : #ifdef CONFIG_COMPAT
58 : #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
59 : /*
60 : * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
61 : * by the compat vectors page.
62 : */
63 : #define TASK_SIZE_32 UL(0x100000000)
64 : #else
65 : #define TASK_SIZE_32 (UL(0x100000000) - PAGE_SIZE)
66 : #endif /* CONFIG_ARM64_64K_PAGES */
67 : #define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
68 : TASK_SIZE_32 : TASK_SIZE_64)
69 : #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
70 : TASK_SIZE_32 : TASK_SIZE_64)
71 : #define DEFAULT_MAP_WINDOW (test_thread_flag(TIF_32BIT) ? \
72 : TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
73 : #else
74 : #define TASK_SIZE TASK_SIZE_64
75 : #define DEFAULT_MAP_WINDOW DEFAULT_MAP_WINDOW_64
76 : #endif /* CONFIG_COMPAT */
77 :
78 : #ifdef CONFIG_ARM64_FORCE_52BIT
79 : #define STACK_TOP_MAX TASK_SIZE_64
80 : #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
81 : #else
82 : #define STACK_TOP_MAX DEFAULT_MAP_WINDOW_64
83 : #define TASK_UNMAPPED_BASE (PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
84 : #endif /* CONFIG_ARM64_FORCE_52BIT */
85 :
86 : #ifdef CONFIG_COMPAT
87 : #define AARCH32_VECTORS_BASE 0xffff0000
88 : #define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
89 : AARCH32_VECTORS_BASE : STACK_TOP_MAX)
90 : #else
91 : #define STACK_TOP STACK_TOP_MAX
92 : #endif /* CONFIG_COMPAT */
93 :
94 : #ifndef CONFIG_ARM64_FORCE_52BIT
95 : #define arch_get_mmap_end(addr, len, flags) \
96 : (((addr) > DEFAULT_MAP_WINDOW) ? TASK_SIZE : DEFAULT_MAP_WINDOW)
97 :
98 : #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
99 : base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
100 : base)
101 : #endif /* CONFIG_ARM64_FORCE_52BIT */
102 :
103 : extern phys_addr_t arm64_dma_phys_limit;
104 : #define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
105 :
106 : struct debug_info {
107 : #ifdef CONFIG_HAVE_HW_BREAKPOINT
108 : /* Have we suspended stepping by a debugger? */
109 : int suspended_step;
110 : /* Allow breakpoints and watchpoints to be disabled for this thread. */
111 : int bps_disabled;
112 : int wps_disabled;
113 : /* Hardware breakpoints pinned to this task. */
114 : struct perf_event *hbp_break[ARM_MAX_BRP];
115 : struct perf_event *hbp_watch[ARM_MAX_WRP];
116 : #endif
117 : };
118 :
119 : enum vec_type {
120 : ARM64_VEC_SVE = 0,
121 : ARM64_VEC_SME,
122 : ARM64_VEC_MAX,
123 : };
124 :
125 : enum fp_type {
126 : FP_STATE_CURRENT, /* Save based on current task state. */
127 : FP_STATE_FPSIMD,
128 : FP_STATE_SVE,
129 : };
130 :
131 : struct cpu_context {
132 : unsigned long x19;
133 : unsigned long x20;
134 : unsigned long x21;
135 : unsigned long x22;
136 : unsigned long x23;
137 : unsigned long x24;
138 : unsigned long x25;
139 : unsigned long x26;
140 : unsigned long x27;
141 : unsigned long x28;
142 : unsigned long fp;
143 : unsigned long sp;
144 : unsigned long pc;
145 : };
146 :
147 : struct thread_struct {
148 : struct cpu_context cpu_context; /* cpu context */
149 :
150 : /*
151 : * Whitelisted fields for hardened usercopy:
152 : * Maintainers must ensure manually that this contains no
153 : * implicit padding.
154 : */
155 : struct {
156 : unsigned long tp_value; /* TLS register */
157 : unsigned long tp2_value;
158 : struct user_fpsimd_state fpsimd_state;
159 : } uw;
160 :
161 : enum fp_type fp_type; /* registers FPSIMD or SVE? */
162 : unsigned int fpsimd_cpu;
163 : void *sve_state; /* SVE registers, if any */
164 : void *sme_state; /* ZA and ZT state, if any */
165 : unsigned int vl[ARM64_VEC_MAX]; /* vector length */
166 : unsigned int vl_onexec[ARM64_VEC_MAX]; /* vl after next exec */
167 : unsigned long fault_address; /* fault info */
168 : unsigned long fault_code; /* ESR_EL1 value */
169 : struct debug_info debug; /* debugging */
170 : #ifdef CONFIG_ARM64_PTR_AUTH
171 : struct ptrauth_keys_user keys_user;
172 : #ifdef CONFIG_ARM64_PTR_AUTH_KERNEL
173 : struct ptrauth_keys_kernel keys_kernel;
174 : #endif
175 : #endif
176 : #ifdef CONFIG_ARM64_MTE
177 : u64 mte_ctrl;
178 : #endif
179 : u64 sctlr_user;
180 : u64 svcr;
181 : u64 tpidr2_el0;
182 : };
183 :
184 : static inline unsigned int thread_get_vl(struct thread_struct *thread,
185 : enum vec_type type)
186 : {
187 : return thread->vl[type];
188 : }
189 :
190 : static inline unsigned int thread_get_sve_vl(struct thread_struct *thread)
191 : {
192 : return thread_get_vl(thread, ARM64_VEC_SVE);
193 : }
194 :
195 : static inline unsigned int thread_get_sme_vl(struct thread_struct *thread)
196 : {
197 : return thread_get_vl(thread, ARM64_VEC_SME);
198 : }
199 :
200 : static inline unsigned int thread_get_cur_vl(struct thread_struct *thread)
201 : {
202 : if (system_supports_sme() && (thread->svcr & SVCR_SM_MASK))
203 : return thread_get_sme_vl(thread);
204 : else
205 : return thread_get_sve_vl(thread);
206 : }
207 :
208 : unsigned int task_get_vl(const struct task_struct *task, enum vec_type type);
209 : void task_set_vl(struct task_struct *task, enum vec_type type,
210 : unsigned long vl);
211 : void task_set_vl_onexec(struct task_struct *task, enum vec_type type,
212 : unsigned long vl);
213 : unsigned int task_get_vl_onexec(const struct task_struct *task,
214 : enum vec_type type);
215 :
216 : static inline unsigned int task_get_sve_vl(const struct task_struct *task)
217 : {
218 : return task_get_vl(task, ARM64_VEC_SVE);
219 : }
220 :
221 : static inline unsigned int task_get_sme_vl(const struct task_struct *task)
222 : {
223 : return task_get_vl(task, ARM64_VEC_SME);
224 : }
225 :
226 : static inline void task_set_sve_vl(struct task_struct *task, unsigned long vl)
227 : {
228 : task_set_vl(task, ARM64_VEC_SVE, vl);
229 : }
230 :
231 : static inline unsigned int task_get_sve_vl_onexec(const struct task_struct *task)
232 : {
233 : return task_get_vl_onexec(task, ARM64_VEC_SVE);
234 : }
235 :
236 : static inline void task_set_sve_vl_onexec(struct task_struct *task,
237 : unsigned long vl)
238 : {
239 : task_set_vl_onexec(task, ARM64_VEC_SVE, vl);
240 : }
241 :
242 : #define SCTLR_USER_MASK \
243 : (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \
244 : SCTLR_EL1_TCF0_MASK)
245 :
246 : static inline void arch_thread_struct_whitelist(unsigned long *offset,
247 : unsigned long *size)
248 : {
249 : /* Verify that there is no padding among the whitelisted fields: */
250 : BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
251 : sizeof_field(struct thread_struct, uw.tp_value) +
252 : sizeof_field(struct thread_struct, uw.tp2_value) +
253 : sizeof_field(struct thread_struct, uw.fpsimd_state));
254 :
255 : *offset = offsetof(struct thread_struct, uw);
256 : *size = sizeof_field(struct thread_struct, uw);
257 : }
258 :
259 : #ifdef CONFIG_COMPAT
260 : #define task_user_tls(t) \
261 : ({ \
262 : unsigned long *__tls; \
263 : if (is_compat_thread(task_thread_info(t))) \
264 : __tls = &(t)->thread.uw.tp2_value; \
265 : else \
266 : __tls = &(t)->thread.uw.tp_value; \
267 : __tls; \
268 : })
269 : #else
270 : #define task_user_tls(t) (&(t)->thread.uw.tp_value)
271 : #endif
272 :
273 : /* Sync TPIDR_EL0 back to thread_struct for current */
274 : void tls_preserve_current_state(void);
275 :
276 : #define INIT_THREAD { \
277 : .fpsimd_cpu = NR_CPUS, \
278 : }
279 :
280 15463975 : static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
281 : {
282 15463975 : s32 previous_syscall = regs->syscallno;
283 15463975 : memset(regs, 0, sizeof(*regs));
284 15463975 : regs->syscallno = previous_syscall;
285 15463975 : regs->pc = pc;
286 :
287 15463975 : if (system_uses_irq_prio_masking())
288 : regs->pmr_save = GIC_PRIO_IRQON;
289 15463975 : }
290 :
291 15463967 : static inline void start_thread(struct pt_regs *regs, unsigned long pc,
292 : unsigned long sp)
293 : {
294 15463967 : start_thread_common(regs, pc);
295 15463939 : regs->pstate = PSR_MODE_EL0t;
296 15463939 : spectre_v4_enable_task_mitigation(current);
297 15463880 : regs->sp = sp;
298 15463880 : }
299 :
300 : #ifdef CONFIG_COMPAT
301 : static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
302 : unsigned long sp)
303 : {
304 : start_thread_common(regs, pc);
305 : regs->pstate = PSR_AA32_MODE_USR;
306 : if (pc & 1)
307 : regs->pstate |= PSR_AA32_T_BIT;
308 :
309 : #ifdef __AARCH64EB__
310 : regs->pstate |= PSR_AA32_E_BIT;
311 : #endif
312 :
313 : spectre_v4_enable_task_mitigation(current);
314 : regs->compat_sp = sp;
315 : }
316 : #endif
317 :
318 : static __always_inline bool is_ttbr0_addr(unsigned long addr)
319 : {
320 : /* entry assembly clears tags for TTBR0 addrs */
321 : return addr < TASK_SIZE;
322 : }
323 :
324 : static __always_inline bool is_ttbr1_addr(unsigned long addr)
325 : {
326 : /* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
327 : return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
328 : }
329 :
330 : /* Forward declaration, a strange C thing */
331 : struct task_struct;
332 :
333 : unsigned long __get_wchan(struct task_struct *p);
334 :
335 : void update_sctlr_el1(u64 sctlr);
336 :
337 : /* Thread switching */
338 : extern struct task_struct *cpu_switch_to(struct task_struct *prev,
339 : struct task_struct *next);
340 :
341 : #define task_pt_regs(p) \
342 : ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
343 :
344 : #define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
345 : #define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
346 :
347 : /*
348 : * Prefetching support
349 : */
350 : #define ARCH_HAS_PREFETCH
351 : static inline void prefetch(const void *ptr)
352 : {
353 1324528625 : asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
354 : }
355 :
356 : #define ARCH_HAS_PREFETCHW
357 : static inline void prefetchw(const void *ptr)
358 : {
359 1896066 : asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
360 : }
361 :
362 : #define ARCH_HAS_SPINLOCK_PREFETCH
363 265574985 : static inline void spin_lock_prefetch(const void *ptr)
364 : {
365 265574985 : asm volatile(ARM64_LSE_ATOMIC_INSN(
366 : "prfm pstl1strm, %a0",
367 : "nop") : : "p" (ptr));
368 265590321 : }
369 :
370 : extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
371 : extern void __init minsigstksz_setup(void);
372 :
373 : /*
374 : * Not at the top of the file due to a direct #include cycle between
375 : * <asm/fpsimd.h> and <asm/processor.h>. Deferring this #include
376 : * ensures that contents of processor.h are visible to fpsimd.h even if
377 : * processor.h is included first.
378 : *
379 : * These prctl helpers are the only things in this file that require
380 : * fpsimd.h. The core code expects them to be in this header.
381 : */
382 : #include <asm/fpsimd.h>
383 :
384 : /* Userspace interface for PR_S[MV]E_{SET,GET}_VL prctl()s: */
385 : #define SVE_SET_VL(arg) sve_set_current_vl(arg)
386 : #define SVE_GET_VL() sve_get_current_vl()
387 : #define SME_SET_VL(arg) sme_set_current_vl(arg)
388 : #define SME_GET_VL() sme_get_current_vl()
389 :
390 : /* PR_PAC_RESET_KEYS prctl */
391 : #define PAC_RESET_KEYS(tsk, arg) ptrauth_prctl_reset_keys(tsk, arg)
392 :
393 : /* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */
394 : #define PAC_SET_ENABLED_KEYS(tsk, keys, enabled) \
395 : ptrauth_set_enabled_keys(tsk, keys, enabled)
396 : #define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
397 :
398 : #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
399 : /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
400 : long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
401 : long get_tagged_addr_ctrl(struct task_struct *task);
402 : #define SET_TAGGED_ADDR_CTRL(arg) set_tagged_addr_ctrl(current, arg)
403 : #define GET_TAGGED_ADDR_CTRL() get_tagged_addr_ctrl(current)
404 : #endif
405 :
406 : #endif /* __ASSEMBLY__ */
407 : #endif /* __ASM_PROCESSOR_H */
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