Line data    Source code

       1             : /* SPDX-License-Identifier: GPL-2.0-only */
       2             : /*
       3             :  * Based on arch/arm/include/asm/mmu_context.h
       4             :  *
       5             :  * Copyright (C) 1996 Russell King.
       6             :  * Copyright (C) 2012 ARM Ltd.
       7             :  */
       8             : #ifndef __ASM_MMU_CONTEXT_H
       9             : #define __ASM_MMU_CONTEXT_H
      10             : 
      11             : #ifndef __ASSEMBLY__
      12             : 
      13             : #include <linux/compiler.h>
      14             : #include <linux/sched.h>
      15             : #include <linux/sched/hotplug.h>
      16             : #include <linux/mm_types.h>
      17             : #include <linux/pgtable.h>
      18             : 
      19             : #include <asm/cacheflush.h>
      20             : #include <asm/cpufeature.h>
      21             : #include <asm/daifflags.h>
      22             : #include <asm/proc-fns.h>
      23             : #include <asm-generic/mm_hooks.h>
      24             : #include <asm/cputype.h>
      25             : #include <asm/sysreg.h>
      26             : #include <asm/tlbflush.h>
      27             : 
      28             : extern bool rodata_full;
      29             : 
      30             : static inline void contextidr_thread_switch(struct task_struct *next)
      31             : {
      32             :         if (!IS_ENABLED(CONFIG_PID_IN_CONTEXTIDR))
      33             :                 return;
      34             : 
      35             :         write_sysreg(task_pid_nr(next), contextidr_el1);
      36             :         isb();
      37             : }
      38             : 
      39             : /*
      40             :  * Set TTBR0 to reserved_pg_dir. No translations will be possible via TTBR0.
      41             :  */
      42             : static inline void cpu_set_reserved_ttbr0_nosync(void)
      43             : {
      44           0 :         unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
      45             : 
      46           0 :         write_sysreg(ttbr, ttbr0_el1);
      47             : }
      48             : 
      49             : static inline void cpu_set_reserved_ttbr0(void)
      50             : {
      51           0 :         cpu_set_reserved_ttbr0_nosync();
      52           0 :         isb();
      53             : }
      54             : 
      55             : void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
      56             : 
      57             : static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm)
      58             : {
      59             :         BUG_ON(pgd == swapper_pg_dir);
      60             :         cpu_do_switch_mm(virt_to_phys(pgd),mm);
      61             : }
      62             : 
      63             : /*
      64             :  * TCR.T0SZ value to use when the ID map is active. Usually equals
      65             :  * TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
      66             :  * physical memory, in which case it will be smaller.
      67             :  */
      68             : extern int idmap_t0sz;
      69             : 
      70             : /*
      71             :  * Ensure TCR.T0SZ is set to the provided value.
      72             :  */
      73             : static inline void __cpu_set_tcr_t0sz(unsigned long t0sz)
      74             : {
      75             :         unsigned long tcr = read_sysreg(tcr_el1);
      76             : 
      77             :         if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz)
      78             :                 return;
      79             : 
      80             :         tcr &= ~TCR_T0SZ_MASK;
      81             :         tcr |= t0sz << TCR_T0SZ_OFFSET;
      82             :         write_sysreg(tcr, tcr_el1);
      83             :         isb();
      84             : }
      85             : 
      86             : #define cpu_set_default_tcr_t0sz()      __cpu_set_tcr_t0sz(TCR_T0SZ(vabits_actual))
      87             : #define cpu_set_idmap_tcr_t0sz()        __cpu_set_tcr_t0sz(idmap_t0sz)
      88             : 
      89             : /*
      90             :  * Remove the idmap from TTBR0_EL1 and install the pgd of the active mm.
      91             :  *
      92             :  * The idmap lives in the same VA range as userspace, but uses global entries
      93             :  * and may use a different TCR_EL1.T0SZ. To avoid issues resulting from
      94             :  * speculative TLB fetches, we must temporarily install the reserved page
      95             :  * tables while we invalidate the TLBs and set up the correct TCR_EL1.T0SZ.
      96             :  *
      97             :  * If current is a not a user task, the mm covers the TTBR1_EL1 page tables,
      98             :  * which should not be installed in TTBR0_EL1. In this case we can leave the
      99             :  * reserved page tables in place.
     100             :  */
     101             : static inline void cpu_uninstall_idmap(void)
     102             : {
     103             :         struct mm_struct *mm = current->active_mm;
     104             : 
     105             :         cpu_set_reserved_ttbr0();
     106             :         local_flush_tlb_all();
     107             :         cpu_set_default_tcr_t0sz();
     108             : 
     109             :         if (mm != &init_mm && !system_uses_ttbr0_pan())
     110             :                 cpu_switch_mm(mm->pgd, mm);
     111             : }
     112             : 
     113             : static inline void __cpu_install_idmap(pgd_t *idmap)
     114             : {
     115             :         cpu_set_reserved_ttbr0();
     116             :         local_flush_tlb_all();
     117             :         cpu_set_idmap_tcr_t0sz();
     118             : 
     119             :         cpu_switch_mm(lm_alias(idmap), &init_mm);
     120             : }
     121             : 
     122             : static inline void cpu_install_idmap(void)
     123             : {
     124             :         __cpu_install_idmap(idmap_pg_dir);
     125             : }
     126             : 
     127             : /*
     128             :  * Load our new page tables. A strict BBM approach requires that we ensure that
     129             :  * TLBs are free of any entries that may overlap with the global mappings we are
     130             :  * about to install.
     131             :  *
     132             :  * For a real hibernate/resume/kexec cycle TTBR0 currently points to a zero
     133             :  * page, but TLBs may contain stale ASID-tagged entries (e.g. for EFI runtime
     134             :  * services), while for a userspace-driven test_resume cycle it points to
     135             :  * userspace page tables (and we must point it at a zero page ourselves).
     136             :  *
     137             :  * We change T0SZ as part of installing the idmap. This is undone by
     138             :  * cpu_uninstall_idmap() in __cpu_suspend_exit().
     139             :  */
     140             : static inline void cpu_install_ttbr0(phys_addr_t ttbr0, unsigned long t0sz)
     141             : {
     142             :         cpu_set_reserved_ttbr0();
     143             :         local_flush_tlb_all();
     144             :         __cpu_set_tcr_t0sz(t0sz);
     145             : 
     146             :         /* avoid cpu_switch_mm() and its SW-PAN and CNP interactions */
     147             :         write_sysreg(ttbr0, ttbr0_el1);
     148             :         isb();
     149             : }
     150             : 
     151             : /*
     152             :  * Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
     153             :  * avoiding the possibility of conflicting TLB entries being allocated.
     154             :  */
     155             : static inline void cpu_replace_ttbr1(pgd_t *pgdp, pgd_t *idmap)
     156             : {
     157             :         typedef void (ttbr_replace_func)(phys_addr_t);
     158             :         extern ttbr_replace_func idmap_cpu_replace_ttbr1;
     159             :         ttbr_replace_func *replace_phys;
     160             :         unsigned long daif;
     161             : 
     162             :         /* phys_to_ttbr() zeros lower 2 bits of ttbr with 52-bit PA */
     163             :         phys_addr_t ttbr1 = phys_to_ttbr(virt_to_phys(pgdp));
     164             : 
     165             :         if (system_supports_cnp() && !WARN_ON(pgdp != lm_alias(swapper_pg_dir))) {
     166             :                 /*
     167             :                  * cpu_replace_ttbr1() is used when there's a boot CPU
     168             :                  * up (i.e. cpufeature framework is not up yet) and
     169             :                  * latter only when we enable CNP via cpufeature's
     170             :                  * enable() callback.
     171             :                  * Also we rely on the system_cpucaps bit being set before
     172             :                  * calling the enable() function.
     173             :                  */
     174             :                 ttbr1 |= TTBR_CNP_BIT;
     175             :         }
     176             : 
     177             :         replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
     178             : 
     179             :         __cpu_install_idmap(idmap);
     180             : 
     181             :         /*
     182             :          * We really don't want to take *any* exceptions while TTBR1 is
     183             :          * in the process of being replaced so mask everything.
     184             :          */
     185             :         daif = local_daif_save();
     186             :         replace_phys(ttbr1);
     187             :         local_daif_restore(daif);
     188             : 
     189             :         cpu_uninstall_idmap();
     190             : }
     191             : 
     192             : /*
     193             :  * It would be nice to return ASIDs back to the allocator, but unfortunately
     194             :  * that introduces a race with a generation rollover where we could erroneously
     195             :  * free an ASID allocated in a future generation. We could workaround this by
     196             :  * freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
     197             :  * but we'd then need to make sure that we didn't dirty any TLBs afterwards.
     198             :  * Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
     199             :  * take CPU migration into account.
     200             :  */
     201             : void check_and_switch_context(struct mm_struct *mm);
     202             : 
     203             : #define init_new_context(tsk, mm) init_new_context(tsk, mm)
     204             : static inline int
     205             : init_new_context(struct task_struct *tsk, struct mm_struct *mm)
     206             : {
     207             :         atomic64_set(&mm->context.id, 0);
     208             :         refcount_set(&mm->context.pinned, 0);
     209             :         return 0;
     210             : }
     211             : 
     212             : #ifdef CONFIG_ARM64_SW_TTBR0_PAN
     213             : static inline void update_saved_ttbr0(struct task_struct *tsk,
     214             :                                       struct mm_struct *mm)
     215             : {
     216             :         u64 ttbr;
     217             : 
     218             :         if (!system_uses_ttbr0_pan())
     219             :                 return;
     220             : 
     221             :         if (mm == &init_mm)
     222             :                 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir));
     223             :         else
     224             :                 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48;
     225             : 
     226             :         WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr);
     227             : }
     228             : #else
     229             : static inline void update_saved_ttbr0(struct task_struct *tsk,
     230             :                                       struct mm_struct *mm)
     231             : {
     232             : }
     233             : #endif
     234             : 
     235             : #define enter_lazy_tlb enter_lazy_tlb
     236             : static inline void
     237             : enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
     238             : {
     239             :         /*
     240             :          * We don't actually care about the ttbr0 mapping, so point it at the
     241             :          * zero page.
     242             :          */
     243             :         update_saved_ttbr0(tsk, &init_mm);
     244             : }
     245             : 
     246    10218876 : static inline void __switch_mm(struct mm_struct *next)
     247             : {
     248             :         /*
     249             :          * init_mm.pgd does not contain any user mappings and it is always
     250             :          * active for kernel addresses in TTBR1. Just set the reserved TTBR0.
     251             :          */
     252    10218876 :         if (next == &init_mm) {
     253           0 :                 cpu_set_reserved_ttbr0();
     254           0 :                 return;
     255             :         }
     256             : 
     257    10218876 :         check_and_switch_context(next);
     258             : }
     259             : 
     260             : static inline void
     261             : switch_mm(struct mm_struct *prev, struct mm_struct *next,
     262             :           struct task_struct *tsk)
     263             : {
     264    10219317 :         if (prev != next)
     265    10219317 :                 __switch_mm(next);
     266             : 
     267             :         /*
     268             :          * Update the saved TTBR0_EL1 of the scheduled-in task as the previous
     269             :          * value may have not been initialised yet (activate_mm caller) or the
     270             :          * ASID has changed since the last run (following the context switch
     271             :          * of another thread of the same process).
     272             :          */
     273    10220692 :         update_saved_ttbr0(tsk, next);
     274             : }
     275             : 
     276             : static inline const struct cpumask *
     277             : task_cpu_possible_mask(struct task_struct *p)
     278             : {
     279             :         if (!static_branch_unlikely(&arm64_mismatched_32bit_el0))
     280             :                 return cpu_possible_mask;
     281             : 
     282             :         if (!is_compat_thread(task_thread_info(p)))
     283             :                 return cpu_possible_mask;
     284             : 
     285             :         return system_32bit_el0_cpumask();
     286             : }
     287             : #define task_cpu_possible_mask  task_cpu_possible_mask
     288             : 
     289             : void verify_cpu_asid_bits(void);
     290             : void post_ttbr_update_workaround(void);
     291             : 
     292             : unsigned long arm64_mm_context_get(struct mm_struct *mm);
     293             : void arm64_mm_context_put(struct mm_struct *mm);
     294             : 
     295             : #define mm_untag_mask mm_untag_mask
     296             : static inline unsigned long mm_untag_mask(struct mm_struct *mm)
     297             : {
     298             :         return -1UL >> 8;
     299             : }
     300             : 
     301             : #include <asm-generic/mmu_context.h>
     302             : 
     303             : #endif /* !__ASSEMBLY__ */
     304             : 
     305             : #endif /* !__ASM_MMU_CONTEXT_H */